50英寸LED背光液晶電視屏結(jié)構(gòu)與電氣接口技術(shù)規(guī)范
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中國(guó)電子視像行業(yè)協(xié)會(huì)標(biāo)準(zhǔn)
CVIA-TJ-LCD/LED-2012-08
50英寸LED背光液晶電視屏結(jié)構(gòu)與電氣接口技術(shù)規(guī)范
(2.0版本)修訂稿
| 2012-x-x發(fā)布 |
| 2012-x-x實(shí)施 |
| 發(fā) 布 |
中國(guó)電子視像行業(yè)協(xié)會(huì)
目 錄
前言………………………………………………………………………………………………………1
1、范圍………………………………………………………………………………………………… 2
2、結(jié)構(gòu)部分…………………………………………………………………………………………… 2
3、電氣接口部分……………………………………………………………………………………… 6
前 言
本規(guī)范是中國(guó)電子視像行業(yè)協(xié)會(huì)的推薦性標(biāo)準(zhǔn)，是協(xié)會(huì)相關(guān)會(huì)員單位在組織技術(shù)研發(fā)、采購和生產(chǎn)過程中的主要參照標(biāo)準(zhǔn)，也推薦其它相關(guān)企業(yè)參考采用。
LED背光液晶電視屏結(jié)構(gòu)與電氣接口技術(shù)規(guī)范，是根據(jù)產(chǎn)業(yè)和市場(chǎng)的發(fā)展需求，由中國(guó)電子視像行業(yè)協(xié)會(huì)(簡(jiǎn)稱“視像協(xié)會(huì)”)組織相關(guān)會(huì)員單位，共同制定的推薦性標(biāo)準(zhǔn)。本規(guī)范旨在為企業(yè)提供彩色電視機(jī)用液晶顯示屏在結(jié)構(gòu)和電氣接口參數(shù)方面的一致性，以達(dá)到降低生產(chǎn)成本、規(guī)范生產(chǎn)秩序、促進(jìn)市場(chǎng)繁榮的目的。
本規(guī)范主要起草單位(排名不分先后)：青島海信電器股份有限公司、廈門華僑電子股份有限公司、TCL集團(tuán)股份有限公司、青島海爾電子有限公司、深圳創(chuàng)維-RGB電子有限公司、四川長(zhǎng)虹電器股份有限公司、康佳集團(tuán)股份有限公司、南京熊貓電子集團(tuán)有限公司。
本規(guī)范V2.0版主要是在V1.0版基礎(chǔ)上增加了對(duì)于更窄邊框屏和3D屏的相關(guān)定義。
本規(guī)范的所有權(quán)、解釋權(quán)和修訂權(quán)屬于中國(guó)電子視像行業(yè)協(xié)會(huì)。
1、范圍
本標(biāo)準(zhǔn)給出了50英寸LED背光液晶電視屏(以下簡(jiǎn)稱為“屏”)的結(jié)構(gòu)和電氣接口技術(shù)規(guī)范，這些規(guī)范是根據(jù)目前中國(guó)市場(chǎng)上被共同認(rèn)可的主流產(chǎn)品規(guī)范而確定。
2、結(jié)構(gòu)部分[1]
2.1 關(guān)于外形長(zhǎng)寬尺寸為1122.64 mm×645.31 mm、兩側(cè)邊框?qū)挾葹?.9mm的屏
2.1.1 屏正面與背面的結(jié)構(gòu)布局示意圖分別見圖1和圖2,結(jié)構(gòu)尺寸圖分別見圖3和圖4(詳細(xì)數(shù)據(jù)見附件4和附件6的2D圖紙)。
2.1.2 屏的外形結(jié)構(gòu)尺寸：
2.1.2.1 外形長(zhǎng)寬尺寸為1122.64 mm×645.31 mm。
2.1.2.2 邊框?qū)挾龋荷稀?側(cè)邊框?yàn)?.9mm，下邊框?yàn)?2mm。
2.1.2.3 側(cè)邊和頂部邊框厚度≤15.1mm，底部邊框厚度≤18.4mm。
2.1.2.4 屏邊框正面到屏玻璃的距離:1.2mm-18mm。
2.1.3 屏背部基本參數(shù)：
2.1.3.1 壁掛采用400×400的標(biāo)準(zhǔn)(為內(nèi)嵌式盲孔螺柱)，壁掛螺柱端面到屏邊框正面的高度
為21.8mm，內(nèi)螺紋M6，螺柱外徑為φ14mm。
2.1.3.2 底座的立柱固定位置：凸包到屏邊框正面的高度為16.4mm，螺孔為M4。屏廠家在開
發(fā)新屏?xí)r，如需更改，應(yīng)第一時(shí)間通知視像協(xié)會(huì)并與起草本規(guī)范的整機(jī)廠溝通，提供合
適的立柱固定位置。
2.1.3.3 固定主板和電源板的螺孔為M3，凸包小端直徑為φ8，大端直徑≤φ20;其它位置的
M4凸包小端直徑為φ12。
2.1.3.4 固定主板的凸包高度：凸包頂面到屏邊框正面的高度為15.8mm。
2.1.3.5 固定電源板的凸包高度：凸包頂面到屏邊框正面的高度為18.3mm。
2.1.3.6 固定音箱的凸包高度：凸包頂面到屏邊框正面的高度為15.8mm。
2.1.3.7 凸包和螺柱安裝孔深度規(guī)格：標(biāo)稱深度≧4.8mm，特殊孔規(guī)格單獨(dú)標(biāo)出。
2.1.4 屏背面螺孔位置如圖4，標(biāo)稱深度≥4.0mm。
2.1.5 屏頂側(cè)和兩側(cè)卡扣方孔(尺寸為12×3) 的位置如圖3，方孔的深度≧2.0mm。
2.1.6 LED Driver板(即Converter板)，位置在圖2左上角，屏廠家可根據(jù)Driver板的大小排布，
但不能干涉到Driver板下面的凸包。
2.1.7 屏的詳細(xì)結(jié)構(gòu)尺寸見附件3的3D圖紙。
圖1 50英寸LED背光液晶電視屏正面結(jié)構(gòu)布局示意圖(9.9mm側(cè)邊框)
圖2 50英寸LED背光液晶電視屏背面結(jié)構(gòu)布局示意圖(9.9mm側(cè)邊框)
圖3 50英寸LED背光液晶電視屏正面結(jié)構(gòu)布局示意圖尺寸圖(9.9mm側(cè)邊框)
圖4 50英寸LED背光液晶電視屏背面結(jié)構(gòu)布局示意圖尺寸圖(9.9mm側(cè)邊框)
3、電氣接口部分
3.1 LED Driver接口定義如下：
| PIN | Symbol | Description |
| 1 | VDDB | Operating Voltage Supply， +24V DC regulated |
| 2 | VDDB | Operating Voltage Supply， +24V DC regulated |
| 3 | VDDB | Operating Voltage Supply， +24V DC regulated |
| 4 | VDDB | Operating Voltage Supply， +24V DC regulated |
| 5 | VDDB | Operating Voltage Supply， +24V DC regulated |
| 6 | BLGND | Ground and Current Return |
| 7 | BLGND | Ground and Current Return |
| 8 | BLGND | Ground and Current Return |
| 9 | BLGND | Ground and Current Return |
| 10 | BLGND | Ground and Current Return |
| 11 | DET | BLU status detection: Normal : 0~0.8V ; Abnormal : Open collector |
| 12 | VBLON | BLU On-Off control: High /Open(3.3V) : BL On ; Low (-0.3~0.8V/GND) : BL Off |
| 13 | VDIM | N.C for no DC dimming. Or Internal PWM (0~3.3V for 20~100% Duty， open for 100%) < NC ; at External PWM mode> |
| 14 | PDIM | External PWM (10%~100% Duty， open for 100%) < NC ;at Internal PWM mode> |
3.2 LVDS接口定義如下：
3.2.1 51-pin的定義(適用于60HZ/120HZ 2D/3D SG/PR屏)：
| PIN | Name | Description |
| 1 | N.C. | No connection |
| 2 | N.C. | No Connection |
| 3 | N.C. | No Connection |
| 4 | N.C. | No Connection |
| 5 | L/R out(SG) | High(3.3V) : L； |
| Low(GND) : R | ||
| or：N.C. | No Connection | |
| 6 | ROTATE | High(3.3V) : Rotate enable(Data mirror)； Open/Low(GND) : Normal |
| or：N.C. | No Connection | |
| 7 | SELLVDS | Open/High(3.3V) for NS， Low(GND) for JEIDA |
| 8 | DCR1 | DCR PWM Dimming Signal Input |
| Duty: TBD%~100% (0~3.3V) | ||
| or：N.C. | No Connection | |
| 9 | DCR2 | DCR PWM Dimming Signal Output |
| Duty: TBD%~100% (0~3.3V) | ||
| or：N.C. | No Connection | |
| 10 | DCR3 | DCR Function ON/OFF Selection |
| Low(GND)/Open : DCR Function Disable(Bypass DIM_IN) | ||
| High(3.3V) : DCR Function Enable | ||
| or：N.C. | No Connection | |
| or:2D/3D （ PR) | High(3.3V) : PR 3D | |
| Low(GND)/ Open : 2D | ||
| 11 | GND | Ground |
| 12 | CH1[0]- | First pixel Negative LVDS differential data input. Pair 0 |
| 13 | CH1[0]+ | First pixel Positive LVDS differential data input. Pair 0 |
| 14 | CH1[1]- | First pixel Negative LVDS differential data input. Pair 1 |
| 15 | CH1[1]+ | First pixel Positive LVDS differential data input. Pair 1 |
| 16 | CH1[2]- | First pixel Negative LVDS differential data input. Pair 2 |
| 17 | CH1[2]+ | First pixel Positive LVDS differential data input. Pair 2 |
| 18 | GND | Ground |
| 19 | CH1CLK- | First pixel Negative LVDS differential clock input. |
| 20 | CH1CLK+ | First pixel Positive LVDS differential clock input. |
| 21 | GND | Ground |
| 22 | CH1[3]- | First pixel Negative LVDS differential data input. Pair 3 |
| 23 | CH1[3]+ | First pixel Positive LVDS differential data input. Pair 3 |
| 24 | CH1[4]- /NC | First pixel Negative LVDS differential data input. Pair 4（10bit） /NC（8bit） |
| 25 | CH1[4]+ /NC | First pixel Positive LVDS differential data input. Pair 4（10bit） /NC（8bit） |
| 26 | 2D/3D(SG) | Input signal for 2D/3D Mode Selection 2.7~3.3V：SG 3D;0~0.7V：2D |
| or：N.C. | No Connection | |
| 27 | L/R in | Input signal for Left Right eye frame synchronous 2.7~3.3V：L;0~0.7V：R |
| or：N.C. | No Connection | |
| 28 | CH2[0]- | Second pixel Negative LVDS differential data input. Pair 0 |
| 29 | CH2[0]+ | Second pixel Positive LVDS differential data input. Pair 0 |
| 30 | CH2[1]- | Second pixel Negative LVDS differential data input. Pair 1 |
| 31 | CH2[1]+ | Second pixel Positive LVDS differential data input. Pair 1 |
| 32 | CH2[2]- | Second pixel Negative LVDS differential data input. Pair 2 |
| 33 | CH2[2]+ | Second pixel Positive LVDS differential data input. Pair 2 |
| 34 | GND | Ground |
| 35 | CH2CLK- | Second pixel Negative LVDS differential clock input. |
| 36 | CH2CLK+ | Second pixel Positive LVDS differential clock input. |
| 37 | GND | Ground |
| 38 | CH2[3]- | Second pixel Negative LVDS differential data input. Pair 3 |
| 39 | CH2[3]+ | Second pixel Positive LVDS differential data input. Pair 3 |
| 40 | CH2[4]- /NC | Second pixel Negative LVDS differential data input. Pair 4（10bit） /NC（8bit） |
| 41 | CH2[4]+ /NC | Second pixel Positive LVDS differential data input. Pair 4（10bit） /NC（8bit） |
| 42 | N.C. | No Connection |
| or：LD_EN | Input signal for Local Diming Enable H(3.3V) /Open: Enable;Low(GND):Disable | |
| 43 | N.C. | No Connection |
| or：SCN (SG) |
SCN_EN L(GND)or Open: Scanning Disable H(3.3V): Scanning Enable |
|
| 44 | GND | Ground |
| 45 | GND | Ground |
| 46 | GND | Ground |
| 47 | N.C. | No Connection |
| 48 | VCC | +12V power supply |
| 49 | VCC | +12V power supply |
| 50 | VCC | +12V power supply |
| 51 | VCC | +12V power supply |
| 3.2.241-pin的定義(適用于120HZ屏)： | ||
| PIN | Symbol | Description |
| 1 | N.C. | No connection |
| 2 | N.C. | No Connection |
| 3 | N.C. | No Connection |
| 4 | N.C. | No Connection |
| 5 | N.C. | No Connection |
| 6 | N.C. | No Connection |
| 7 | Reserved | Internal Use Only (NC) |
| 8 | N.C. | No Connection |
| 9 | GND | Ground |
| 10 | CH3[0]- | Third pixel Negative LVDS differential data input. Pair 0 |
| 11 | CH3[0]+ | Third pixel Positive LVDS differential data input. Pair 0 |
| 12 | CH3[1]- | Third pixel Negative LVDS differential data input. Pair 1 |
| 13 | CH3[1]+ | Third pixel Positive LVDS differential data input. Pair 1 |
| 14 | CH3[2]- | Third pixel Negative LVDS differential data input. Pair 2 |
| 15 | CH3[2]+ | Third pixel Positive LVDS differential data input. Pair 2 |
| 16 | GND | Ground |
| 17 | CH3CLK- | Third pixel Negative LVDS differential clock input. |
| 18 | CH3CLK+ | Third pixel Positive LVDS differential clock input. |
| 19 | GND | Ground |
| 20 | CH3[3]- | Third pixel Negative LVDS differential data input. Pair 3 |
| 21 | CH3[3]+ | Third pixel Positive LVDS differential data input. Pair 3 |
| 22 | CH3[4]- /NC | Third pixel Negative LVDS differential data input. Pair 4（10bit） /NC（8bit） |
| 23 | CH3[4]+ /NC | Third pixel Positive LVDS differential data input. Pair 4（10bit） /NC（8bit） |
| 24 | GND | Ground |
| 25 | GND | Ground |
| 26 | CH4[0]- | Fourth pixel Negative LVDS differential data input. Pair 0 |
| 27 | CH4[0]+ | Fourth pixel Positive LVDS differential data input. Pair 0 |
| 28 | CH4[1]- | Fourth pixel Negative LVDS differential data input. Pair 1 |
| 29 | CH4[1]+ | Fourth pixel Positive LVDS differential data input. Pair 1 |
| 30 | CH4[2]- | Fourth pixel Negative LVDS differential data input. Pair 2 |
| 31 | CH4[2]+ | Fourth pixel Positive LVDS differential data input. Pair 2 |
| 32 | GND | Ground |
| 33 | CH4CLK- | Fourth pixel Negative LVDS differential clock input. |
| 34 | CH4CLK+ | Fourth pixel Positive LVDS differential clock input. |
| 35 | GND | Ground |
| 36 | CH4[3]- | Fourth pixel Negative LVDS differential data input. Pair 3 |
| 37 | CH4[3]+ | Fourth pixel Positive LVDS differential data input. Pair 3 |
| 38 | CH4[4]- /NC | Fourth pixel Negative LVDS differential data input. Pair 4（10bit） /NC（8bit） |
| 39 | CH4[4]+ /NC | Fourth pixel Positive LVDS differential data input. Pair 4（10bit） /NC（8bit） |
| 40 | GND | Ground |
| 41 | GND | Ground |
備注：120Hz按照First、Second、Third、Fourth對(duì)應(yīng)奇、偶、奇、偶像素順序;
60Hz按照First、Second對(duì)應(yīng)奇、偶像素順序。
3.3 電源和信號(hào)時(shí)序定義(屏?xí)r序包含下列參數(shù)信息)
3.31 LCD驅(qū)動(dòng)電路時(shí)序(LCD Driving Circuit)定義如圖7
圖7 50英寸LED背光液晶電視屏LCD驅(qū)動(dòng)電路時(shí)序
3.3.2 LED背光驅(qū)動(dòng)時(shí)序(Sequence for LED Driver)定義如圖8
圖8 50英寸LED背光液晶電視屏LED背光驅(qū)動(dòng)時(shí)序
3.4 屏的SPEC中須對(duì)LED Driver接口以及LVDS接口中的全部控制端口進(jìn)行功能簡(jiǎn)述、阻抗特性、 端口電壓(或者波形)特性等進(jìn)行明確定義，并同時(shí)提供端口電路簡(jiǎn)圖(示例如下表)。
| Symbol | 功能簡(jiǎn)述 | 阻抗特性 | I/O Type | 端口電壓特性 | 端口電路簡(jiǎn)圖 |
| SCL | EEPROM Serial Clock (for local dimming demo function) | Open Drain Resistor to GND ≥100Kohm | I/O | 0V~3.3V | |
| SDA | EEPROM Serial Data (for local dimming demo function) | Open Drain Resistor to GND ≥100Kohm | I/O | 0V~3.3V | |
| L/R_O | Output signal for Left Right Glasses control | ≤1.1Kohm | O | 0V~0.7V →Right signal, 2.7V~ 3.3V →Left signal | |
| SELLVDS | Input signal for LVDS Data Format Selection | Resistor to GND ≥100Kohm | I | 0V~0.7V→JEDIA, 2.7V~3.3V/OPEN→ VESA | |
| 2D/3D | Input signal for 2D/3D Mode Selection | Resistor to GND ≥15Kohm | I | 0V~0.7V →2D mode, 2.7V ~ 3.3V →3D mode | |
| L/R | Input signal for Left Right eye frame synchronous | Resistor to GND ≥15Kohm | I | 0V~0.7V →Right signal, 2.7V~3.3V →Left signal | |
| LD_EN | Input signal for Local Dimming Enable | Resistor to GND ≥50Kohm | I | 0V~0.7V -->Disable, 2.7V~3.3V/Open --> Enable | |
| SCN_EN | Input signal for Scanning Enable | Resistor to GND ≥50Kohm | I | 0V~0.7V/Open→Disable, 2.7V ~ 3.3V →Enable |
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